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IMP8 1 1 , IMP81 2
POWER MANAGEMENT
4-Pin P Volt ag e Super visor wit h Manual R eset
The IMP811/IMP812 are low-power supervisors designed to monitor voltage levels of 3.0V, 3.3V and 5.0V power supplies in low-power microprocessor (P), microcontroller (C) and digital systems. Each features a debounced manual reset input. The IMP811/812 are improved drop-in replacements for the Maxim MAX811/812 with extended temperature specifications to 105C. A reset signal is issued if the power supply voltage drops below a preset threshold and is asserted for at least 140ms after the supply has risen above the reset threshold. The IMP811 has an active-low output RESET that is guaranteed to be in the correct state for VCC down to 1.1V. The IMP812 has an active-high output RESET. The reset comparator is designed to ignore fast transients on VCC . Low power consumption makes the IMP811/IMP812 ideal for use in portable and battery-operated equipment. Available in a compact 4-pin SOT143 package, the devices use minimal board space. Six voltage thresholds are available to support 3V to 5V systems:
Key Features
x Improved Maxim MAX811/MAX812 replacement -- Specified to 105C -- New 4.0V threshold option x 6A supply current x Monitor 5V, 3.3V and 3V supplies x Manual reset input x 140ms min. reset pulse width x Guaranteed over temperature x Active-LOW reset valid with 1.1V supply (IMP811) x Small 4-pin SOT-143 package x No external components x Power-supply transient-immune design
Reset Threshold Suffix Voltage (V)
L M J T S R 4.63 4.38 4.00 3.08 2.93 2.63
Applications
x x x x x x Computers and controllers Embedded controllers Battery operated systems Intelligent instruments Wireless communication systems PDAs and handheld equipment
Block Diagrams
VCC VCC
IMP811 (IMP812)
MR Manual Reset RESET (RESET) GND
VCC C or P RESET Input GND
811/12_01.eps
IMP, Inc.
San Jose, CA
408-432-9100/www.impweb.com
IMP8 1 1 , IMP81 2
Pin Configuration
SOT143
GND
1 IMP811 (IMP812)
4
VCC
(RESET) RESET
2
3
MR
811/12_02.eps
Ordering Information
Part Number 1 Reset Threshold (V) Temperature Range IMP811 Active LOW Reset with Active LOW Manual Reset
IMP811LEUS-T IMP811MEUS-T IMP811JEUS-T IMP811TEUS-T IMP811SEUS-T IMP811REUS-T IMP812LEUS-T IMP812MEUS-T IMP812JEUS-T IMP812TEUS-T IMP812SEUS-T IMP812REUS-T 4.63 4.38 4.00 3.08 2.93 2.63 4.63 4.38 4.00 3.08 2.93 2.63 - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C - 40C to +105C
Pin-Package
4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143 4-SOT143
Package Marking2 (XX Lot Code)
AMXX ANXX AOXX APXX AQXX ARXX ASXX ATXX AUXX AVXX AWXX AXXX
IMP812 Active HIGH Reset with Active LOW Manual Reset
Notes:
1. Tape and Reel packaging is indicated by the -T designation. 2. Devices may also be marked with full part number: 811L, 812M etc. XX refers to lot.
Absolute Maximum Ratings
Pin Terminal Voltage with Respect to Ground VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V RESET, R SET and R . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) E M Input Current at VCC and R . . . . . . . . . . . 20mA M Output Current: RESET orR SET . . . . . . 20mA E Rate of Rise at VCC . . . . . . . . . . . . . . . . . . . . 100V/s These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability 2 Power Dissipation (TA = 70C) . . . . . . . . . . 320mW (Derate SOT-143 4mW/C above 70C) Operating Temperature Range . . . . . . . . . . -40C to 105C Storage Temperature Range . . . . . . . . . . . . . -65C to 160C Lead Temperature (soldering, 10 sec) . . . . . 300C
IMP8 1 1 , IMP8 1 2
Electrical Characteristics
Unless otherwise noted VCC is over the full voltage range, TA = -40C to 105C. Typical values at TA = 25C, VCC = 5V for L/M/J devices, VCC = 3.3V for T/S devices and VCC = 3V for R devices.
Parameter
Input Voltage (VCC) Range Supply Current (Unloaded)
Symbol Conditions
VCC ICC TA = 0C to 70C TA = - 40C to 105C TA = - 40C to 85C TA = - 40C to 85C TA = 85C to 105C TA = 85C to 105C L devices VCC < 5.5V, L/M/J VCC < 3.6V, R/S/T VCC < 5.5V, L/M/J VCC < 3.6V, R/S/T TA = 25C TA = - 40C to 85C TA = 85C to 105C TA = 25C TA = - 40C to 85C TA = 85C to 105C TA = 25C TA = - 40C to 85C TA = 85C to 105C TA = 25C TA = - 40C to 85C TA = 85C to 105C TA = 25C TA = - 40C to 85C TA = 85C to 105C TA = 25C TA = - 40C to 85C TA = 85C to 105C
Min
1.1 1.2
Typ
6 5
Max
5.5 5.5 15 10 25 20 4.70 4.75 4.86 4.45 4.50 4.56 4.06 4.10 4.20 3.11 3.15 3.23 2.96 3.00 3.08 2.66 2.70 2.76
Units
V A
Reset Threshold
VTH
M devices
J devices
T devices
S devices
R devices
4.56 4.50 4.40 4.31 4.25 4.16 3.93 3.89 3.80 3.04 3.00 2.92 2.89 2.85 2.78 2.59 2.55 2.50
4.63
V
4.38
4.00
3.08
2.93
2.63
Reset Threshold Temp. Coefficient VCC to Reset Delay Reset Active Timeout Period MR Minimum Pulse Width MR Glitch Immunity MR to RESET Propagation Delay MR Input Threshold
TCVTH VCC = VTH to (VTH - 125mV), L/M/J devices VCC = VTH to (VTH - 125mV), R/S/T devices TA = 0C to 70C TA = - 40C to 105C Note 3 Note 2 VCC > VTH (MAX), IMP811/812L/M/J VCC > VTH (MAX), IMP811/812R/S/T
30 40 20 140 100 10 100 0.5 2.3 0.8 0.7VCC 10 20 0.25VCC 30 0.3 0.4 0.3 560 840
ppm/C s ms s ns s V
VOL tMR tMD VIH VIL VIH VIL VOL
MR Pull-up Resistance Low RESET Output Voltage (IMP811)
High RESET Output Voltage (IMP811) Low RESET Output Voltage (IMP812) High RESET Output Voltage (IMP812)
VOH VOL VOH
VCC = VTH min., ISINK = 1.2mA, IMP811R/S/T VCC = VTH min., ISINK = 3.2mA, IMP811L/M/J VCC > 1.1V, ISINK = 50A VCC > VTH max., ISOURCE = 500A, IMP811R/S/T 0.8VCC VCC > VTH max., ISOURCE = 800A, IMP811L/M/J VCC -1.5 VCC = VTH max., ISINK = 1.2mA, IMP812R/S/T VCC = VTH max., ISINK = 3.2mA, IMP812L/M/J 1.8V < VCC < VTH min., ISOURCE = 150A 0.8VCC
k V
V 0.3 0.4 V V
Notes:
1. Production testing done at TA = 25C. Over temperature specifications guaranteed by design only using six sigma design limits. 2. R SE output is active LOW for the IMP811 and RESET output is active HIGH for the IMP812. E T 3. Glitches of 100ns or less typically will not generate a reset pulse.
3
IMP8 1 1 , IMP81 2
Pin Descriptions
Pin Number
1 2 (IMP811) 2 (IMP812) 3
Name
GND RESET
Function
Ground RESET is asserted LOW if VCC falls below the reset threshold and remains LOW for the 140ms minimum after the reset conditions are removed. In addition, RESET is active LOW as long as the manual reset is low. RESET is asserted HIGH if VCC falls below the reset threshold and remains HIGH for the 140ms minimum after the reset conditions are removed. In addition, RESET is active HIGH as long as the manual reset is low. Manual Reset Input. A logic LOW on MR asserts RESET. RESET remains active as long as MR is LOW and for 180ms after MR returns HIGH. The active low input has an internal 20k pull-up resistor. The input should be left open if not used. It can be driven by TTL or CMOS logic or shorted to ground by a switch.. Power supply input voltage (3.0V, 3.3V, 5.0V)
RESET
MR
4
VCC
Related Products
IMP809
Max. Supply Current Package Pins Manual RESET input Package Type Active-HIGH RESET output Active-LOW RESET output 15A 3 SOT-23 s
IMP810
15A 3 SOT-23 s
IMP811
15A 4 s SOT-143 s
IMP812
15A 4 s SOT-143 s
4
IMP8 1 1 , IMP8 1 2
Detailed Description
Reset Timing and Manual Reset (MR)
The reset signal is asserted-LOW for the IMP811 and HIGH for the IMP812 - when the VCC signal falls below the threshold trip voltage and remains asserted for 140ms minimum after the VCC has risen above the threshold. A logic low on MR asserts RESET LOW on the IMP811 and HIGH on the IMP812. MR is internally pulled high through a 20k resistor and can be driven by TTL/CMOS gates or with open collector/drain outputs. MR can be left open if not used. MR may be connected to a normally-open switch connected to ground without an external debounce circuit. For added noise rejection, a 0.1F capacitor from MR to Ground can be added.
5V VCC 0V
VTH Active Reset Timeout Period 140ms minimum
5V MR 0V Active Reset Timeout Period
5V RESET 0V 5V RESET 0V
811/12_03.eps
IMP811
IMP812
Figure 1. Reset Timing and Manual Reset (MR)
5
IMP8 1 1 , IMP81 2
Application Information
RESET Output Operation
In P/C systems it is important to have the processor begin operation from a known state or be able to return the system to a known state. A RESET output to a processor is provided to prevent improper operation during power supply sequencing or low voltage - brownout - conditions. The IMP811/812 are designed to monitor the system power supply voltages and issue a RESET signal when levels are out of range. RESET outputs are guaranteed to be active for VCC above 1.1V. When VCC exceeds the reset threshold, an internal timer keeps RESET active for the reset timeout period, after which RESET becomes inactive (HIGH for the IMP811 and LOW for the IMP812). If VCC drops below the reset threshold, RESET automatically becomes active. Alternatively, external circuitry or a human operator can initiate this condition using the Manual Reset (MR) pin. There is an internal pullup on MR so it can be left open if it is not used. MR can be driven by TTL/CMOS logic or even an external switch, since it is already debounced. If the switch is at the end of a long cable, it might require a bypass (100nF) at the pin if noise pickup is a problem. Six voltage thresholds are available to support 3V and 5V systems:
Reset Threshold Suffix Voltage (V)
L M J T S R 4.63 4.38 4.00 3.08 2.93 2.63
Valid Reset with VCC under 1.1V
To ensure that logic inputs connected to the IMP811 RESET pin are in a known state when VCC is under 1.1V, a 100k pull-down resistor at RESET is needed. The value is not critical. A similar pull-up resistor to VCC is needed with the IMP812.
Negative VCC Transients
Typically short duration transients of 100mV amplitude and 20s duration do not cause a false RESET. A 0.1F capacitor at VCC increases transient immunity.
VCC
VCC 100k
Power Supply MR
IMP811
RESET GND 100k
Power Supply
IMP812
MR RESET GND
811/12_04.eps
811/12_05.eps
Figure 2. RESET Valid with VCC Under 1.1V
Figure 3. RESET Valid with VCC Under 1.1V
6
IMP8 1 1 , IMP8 1 2
Bi-directional Reset Pin Interfacing
The IMP811/812 can interface with P/C bi-directional reset pins by connecting a 4.7k resistor in series with the IMP809/810 reset output and the P/C bi-directional reset pin.
BUF Buffered RESET
VCC
Power Supply
IMP811
4.7k MR RESET GND
Bi-directional I/O Pin (Example: 68HC11)
C or P RESET Input GND
811/12_06.eps
Figure 4. Bi-directional Reset Pin Interface
Plastic SOT-143 (4-Pin) Inches
B e1
Package Dimensions
Millimeters Max Min Max Plastic SOT-143 (4-Pin)
0.047 0.005 0.022 0.038 0.006 0.120 0.055 0.080 0.079 0.098 0.012 0.787 0.025 0.356 0.762 0.086 2.667 1.194 1.778 1.803 2.083 0.102 1.194 0.127 0.559 0.965 0.152 3.048 1.397 2.032 2.007 2.489 0.305
Min
A
E H
0.031 0.001 0.014 0.030 0.0034 0.105 0.047 0.070 0.071 0.082 0.004
A1 B B1
B1 e D A a = 0-8
C D E e e1 H I
SOT-143 (4-Pin).eps
A1
e
C
L
7
IMP8 1 1 , IMP81 2
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 Fax-on-Demand: 1-800-249-1614 (USA) Fax-on-Demand: 1-303-575-6156 (International) e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 1998 IMP, Inc. Printed in USA Preliminary Part No.: IMP811-812 Document Number: IMP811-6-6/98
8

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